Synthesis Techniques and Optimizations for Reconfigurable Systems

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Springer Science & Business Media, 2003 M10 27 - 245 pages
Synthesis Techniques and Optimization for Reconfigurable Systems discusses methods used to model reconfigurable applications at the system level, many of which could be incorporated directly into modern compilers. The book also discusses a framework for reconfigurable system synthesis, which bridges the gap between application-level compiler analysis and high-level device synthesis. The development of this framework (discussed in Chapter 5), and the creation of application analysis which further optimize its output (discussed in Chapters 7, 8, and 9), represent over four years of rigorous investigation within UCLA's Embedded and Reconfigurable Laboratory (ERLab) and UCSB's Extensible, Programmable and Reconfigirable Embedded SystemS (ExPRESS) Group. The research of these systems has not yet matured, and we continually strive to develop data and methods, which will extend the collective understanding of reconfigurable system synthesis.
Synthesis Techniques and Optimization for Reconfigurable Systems assumes a basic understanding of logic design, hardware synthesis (from high-level architecture generation down to placement and routing), and the structure and form of high-level application constructs (such as loops and branches). However, this book may be read and used in the absence of such background knowledge. This text is aimed at researchers and system-level designers (both academic and industrial), but could easily be used as the text of graduate-level course on reconfigurable system synthesis techniques.

From inside the book

Contents

INTRODUCTION
1
SYNTHESIS OF DIGITAL SYSTEMS
5
RECONFIGURABLE SYSTEMS
15
MODELS OF COMPUTATION
55
A FRAMEWORK FOR SYSTEM SYNTHESIS
85
HARDWARESOFTWARE SYSTEM PARTITIONING
107
INSTRUCTION GENERATION
127
DATA COMMUNICATION
175
INCREASING HARDWARE PARALLELISM
213
Acknowledgments
221
References
222
Index
243
Copyright

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Page 223 - JR Hauser and J. Wawrzynek. GARP: A mips processor with a reconfigurable coprocessor.
Page 223 - N. Park and AC Parker. Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications. IEEE Trans, on CAD, 7(3), 1988. [16] P. Pochmuller, M. Glesner, and F. Longsen. High-Level Synthesis Transformations for Programmable Architectures. EuroDAC '93, 1993. [17] R. Potasman, J. Lis, A. Nicolau, and D. Gajski. Percolation Based Synthesis.

About the author (2003)

Majid Sarrafzadeh is the Director of the Embedded and Reconfigurable Systems Laboratory and a Professor in the Computer Science Department at UCLA.

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