Advances in Computers: Architectural Advances

Front Cover
Marvin Zelkowitz
Elsevier, 2011 M09 21 - 342 pages

The series covers new developments in computer technology. Most chapters present an overview of a current subfield within computers, with many citations, and often include new developments in the field by the authors of the individual chapters. Topics include hardware, software, theoretical underpinnings of computing, and novel applications of computers. This current volume emphasizes architectural advances and includes five chapters on hardware development, games for mobile devices such as cell phones, and open source software development.

The book series is a valuable addition to university courses that emphasize the topics under discussion in that particular volume as well as belonging on the bookshelf of industrial practitioners who need to implement many of the technologies that are described.

  • Current information on power requirements for new processors
  • Development of games for devices with limited screen sizes (e.g. cellular telephones)
  • Open source software development
  • Multicore processors

From inside the book

Contents

Chapter 2 Designing Computational Clusters for Performance and Power
89
Chapter 3 CompilerAssisted Leakage Energy Reduction for Cache Memories
155
Challenges and Opportunities
191
Recent Research Results and Methods
243
Author Index
297
Subject Index
307
Contents of Volumes in this Series
319
Copyright

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Page 1 - Department of Computer Science and Engineering University of California, San Diego, La Jolla, CA 92093-0114 The testability of a VLSI design is strongly affected by its register-transfer level (RTL) structure.
Page 245 - The remainder of this chapter is organized as follows. The next section discusses the various theories of trade.
Page xi - Professor in the Computer Science and Engineering Department at the University of California, San Diego.
Page 152 - Hsu and U. Kremer. The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction.
Page 86 - T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, October 2002.
Page 83 - Brooks D., Tiwari V., Martonosi M., "Wattch: a framework for architectural-level power analysis and optimizations", in: Proceedings of the 27th International Symposium on Computer Architecture (ISCA).
Page 86 - Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor.
Page ix - He is a member of the IEEE and the IEEE Computer Society.
Page 83 - Cache coherence protocols: evaluation using a multiprocessor simulation model," ACM Transactions on Computer Systems, Vol.
Page 150 - D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations.

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